JOB DESCRIPTION:
Will Develop & maintain front End ASIC CAD flows and develop key new methodologies to support Language VHDL/Verilog Synthesis and Simulation.

REQUIRED SKILLS:
Experience with Synopsys Design Compiler and Prime time Timing Analysis essential.
Knowledge of VHDL/Verilog desired. Good Understanding of Key concepts in RTL design & verification.
Qualifications include a BSEE and 3-8 yr. of relevant (semiconductor) industry experience.
Working knowledge of PERL/ Shell scripts required.

Experience with C++/C Preferred. MSEE preferred.

COMMENTS:

DATE POSTED:

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